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Jamie Little
Part IA Michaelmas Term

MOSFET Operation

What is a MOSFET?

MOSFET stands for Metal-Oxide-Semiconductor Field-Effect Transistor. It is the fundamental building block of virtually all modern digital integrated circuits. The name describes its physical structure: a metal (or polysilicon) gate electrode is separated from a semiconductor substrate by a thin insulating oxide layer. The gate voltage creates an electric field that controls the flow of current between two other terminals, hence “field-effect transistor”.

n-channel enhancement-mode MOSFET structure

Consider the n-channel (n-MOS) enhancement-mode transistor that is the workhorse of digital logic:

  • Substrate: p-type silicon.
  • Source (S): an n-type region diffused into the substrate.
  • Drain (D): another n-type region diffused into the substrate.
  • Gate (G): a conducting layer (metal or heavily doped polysilicon) separated from the substrate by a very thin silicon dioxide (SiO₂) insulator layer.

The device is called enhancement mode because at V_GS = 0 (zero gate-to-source voltage), there is no conductive channel between source and drain: the transistor is OFF. A positive gate voltage must be applied to “enhance” the channel and turn it ON. This is the type used in digital logic. (Depletion-mode devices exist but are not relevant to the Tripos.)

OFF state (V_GS < V_T)

When the gate voltage is low (below the threshold voltage V_T), the transistor is OFF. Why?

The source and drain are n-type regions embedded in a p-type substrate. At each S/D boundary with the substrate, there is a p-n junction. In normal operation, these junctions are reverse-biased (the substrate is tied to ground, source and drain are at positive voltages). No current can flow through reverse-biased junctions: there is no continuous path from source to drain.

The region under the gate is still p-type, so there are essentially no free electrons available to carry current. I_DS ≈ 0.

ON state (V_GS > V_T)

When the gate voltage exceeds the threshold voltage V_T, the gate acts like one plate of a capacitor, with the substrate as the other plate. The positive gate voltage repels holes in the p-type substrate and attracts free electrons (minority carriers in the p-type material) to the surface directly under the gate.

When enough electrons accumulate, this thin surface layer inverts from p-type to n-type. This is called the inversion layer or channel. The threshold voltage V_T is the minimum gate voltage needed to form an inversion layer strong enough to allow significant conduction.

With the inversion layer present, there is now a continuous n-type path from source to drain. Electrons can flow from source to drain (conventional current flows from drain to source), and the transistor is ON.

The threshold voltage V_T is typically 0.3V to 0.7V for modern transistors, but in the examples in the course we use a higher V_T of around 1-2V for pedagogical clarity.

p-channel MOSFET (p-MOS)

A p-channel MOSFET is the complement. The substrate is n-type, and the source and drain are p-type regions. The device is ON when V_GS is negative (gate voltage lower than source voltage), which attracts holes to form a p-type inversion channel. Current is carried by holes.

The p-MOS symbol has the same structure but with the gate bubble or inversion dot indicating opposite logic. For digital logic: the p-MOS is ON when its gate is LOW (logic 0), and OFF when its gate is HIGH (logic 1). This is the key to CMOS logic (see /modules/digital-electronics/12-transistors-and-cmos-logic/03-cmos-inverter/).

I-V characteristics

The drain current I_DS is a function of both V_GS and V_DS. There are two operating regions:

Triode (linear) region (V_DS < V_GS - V_T): The transistor behaves roughly like a voltage-controlled resistor. I_DS is approximately proportional to V_DS. For digital purposes, this is the region where the transistor acts as a decent closed switch with some on-resistance R_DS(on).

Saturation region (V_DS > V_GS - V_T): The channel is “pinched off” near the drain. I_DS becomes nearly independent of V_DS and is controlled primarily by V_GS. The transistor behaves approximately like a voltage-controlled current source. For digital switching, we spend little time here: the transistor transitions rapidly through this region only during switching.

The course does not require detailed equations for these regions. What matters:

  1. V_GS < V_T → transistor OFF (open circuit).
  2. V_GS > V_T → transistor ON (low resistance path).
  3. The n-MOS conducts best when pulling the output LOW (to 0V). It is poor at pulling HIGH because as V_out rises, V_GS (difference between fixed gate voltage and rising output) decreases, eventually falling below V_T and turning off.
  4. The p-MOS has the complementary property: it conducts best when pulling HIGH.

MOSFET as a switch

For digital logic analysis, the MOSFET is treated as a voltage-controlled switch:

  • n-MOS: switch closed (ON) when gate = HIGH (logic 1); switch open (OFF) when gate = LOW (logic 0).
  • p-MOS: switch closed (ON) when gate = LOW (logic 0); switch open (OFF) when gate = HIGH (logic 1).

This switch model is sufficient for analysing all CMOS gate circuits (see /modules/digital-electronics/12-transistors-and-cmos-logic/04-cmos-gates/) and for the n-MOS inverter analysis (see /modules/digital-electronics/12-transistors-and-cmos-logic/02-nmos-inverter/).

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