Instruction Execution

Instruction format

The example processor in the course uses a simple fixed-length instruction format. Each instruction is 16 bits, divided into fields:

Field	Bits	Purpose
opcode	top 3 bits	Determines the operation (ADD, LOAD, STORE, BEQZ)
rd	next 3 bits	Destination register
rs1	next 3 bits	First source register
rs2	next 3 bits	Second source register (or immediate offset)

For example, ADD R1, R2, R3 is encoded as:

opcode=010  rd=001  rs1=010  rs2=011

The remaining bits may be used for larger immediates or as part of the opcode for instructions that need different field layouts.

Important convention: the opcode specifies the ALU function for R-type instructions. For LOAD and STORE, the ALU is used to compute the memory address, typically by passing through or adding the register value to an offset. For BEQZ, the ALU tests the register for zero.

Instruction types

R-type: Register-to-register ALU operations

Instruction: ADD R1, R2, R3 (R1 ← R2 + R3).

Execution steps (single-cycle):

1. Fetch: PC → instruction memory → instruction word.
2. Decode: opcode=010, rd=R1, rs1=R2, rs2=R3. The control unit generates signals for register read (R2, R3), ALU operation = ADD, register write enable.
3. Execute: Read R2 and R3 from register file. ALU computes R2 + R3.
4. Writeback: Result written to R1 in the register file.

Control signals needed: ALUsrc=0 (use register value, not immediate), ALUop=ADD, RegWrite=1, MemRead=0, MemWrite=0, MemtoReg=X (don’t care), PCSrc=0 (PC → PC+1).

Memory access: LOAD

Instruction: LOAD R1, [R2] (R1 ← mem[R2]).

Execution steps:

1. Fetch: PC → instruction memory.
2. Decode: opcode indicates LOAD. Read R2 (contains the memory address). R1 is the destination.
3. ALU computes address: pass R2 through the ALU (or add zero offset) to produce the memory address.
4. Memory read: address → data memory, data word read out.
5. Writeback: memory data → register file, written to R1.

Control signals: ALUsrc=0 (R2 passed through ALU), ALUop=PASS, RegWrite=1, MemRead=1, MemWrite=0, MemtoReg=1 (write data comes from memory, not ALU), PCSrc=0.

Note: rs1 is not needed; the instruction preferably uses rs2 for the base address.

Memory access: STORE

Instruction: STORE R1, [R2] (mem[R2] ← R1).

Execution steps:

1. Fetch: PC → instruction memory.
2. Decode: read R1 (data to store) and R2 (memory address).
3. ALU computes address from R2.
4. Memory write: R1’s value written to data memory at the computed address.
5. No writeback to register file.

Control signals: ALUsrc=0, ALUop=PASS, RegWrite=0, MemRead=0, MemWrite=1, MemtoReg=X, PCSrc=0.

Branch: BEQZ

Instruction: BEQZ R1, +10 (if R1=0, PC ← PC+10; else PC ← PC+1).

Execution steps:

1. Fetch, then read R1.
2. ALU tests R1 for zero (subtract 0 from R1, check zero flag).
3. If zero flag set AND opcode is BEQZ: the branch MUX selects the branch target (PC + offset) as the next PC. The offset must be sign-extended and added to the current PC value.
4. If zero flag not set: PC ← PC+1 (sequential execution).

Control signals: ALUsrc=0, ALUop=SUB (or test-zero), RegWrite=0, MemRead=0, MemWrite=0, MemtoReg=X, PCSrc = (opcode==BEQZ AND zero_flag).

The branch target is computed by a separate adder (the “jump” adder) that adds a sign-extended offset to the current PC. In a single-cycle processor, there are separate logic units for PC+1 and PC+offset; in a multicycle processor, the main ALU can be reused for this.

The instruction decoder’s output

The instruction decoder is purely combinational in a single-cycle design. From the opcode bits, it generates:

Signal	Meaning	Width
ALUop	Selects ALU operation	3-4 bits
ALUsrc	0 = register, 1 = immediate	1 bit
RegWrite	Write enable for register file	1 bit
MemRead	Read enable for data memory	1 bit
MemWrite	Write enable for data memory	1 bit
MemtoReg	0 = ALU result, 1 = memory data	1 bit
PCSrc	0 = PC+1, 1 = branch target	1 bit

These control signals configure the datapath for each instruction. The same set of control signals is used across single-cycle, multicycle, and pipelined designs, though the timing of when they are active differs.

See /modules/digital-electronics/13-processor-architecture/04-single-cycle-processor/ for how this all fits together in one clock cycle, and /modules/digital-electronics/13-processor-architecture/05-multicycle-processor/ for the alternative approach.