Microarchitecture: Datapath and Control | Digital Electronics

The two interacting parts

Every processor microarchitecture consists of two interacting subsystems:

Datapath: The data-processing engine. It contains the registers (including the PC), ALU, multiplexers (for selecting between different data sources), and the memory interface. It operates on words of data (e.g., 16-bit or 32-bit values). The datapath provides the capability to perform operations. It is a configurable network of functional units connected by wires and multiplexers.

Control unit: The brain. It receives the current instruction opcode from the datapath and generates control signals that configure the datapath for each instruction:

Which registers to read from the register file.
Which ALU operation to perform (add, subtract, AND, OR, pass-through).
Whether to write the result back to the register file (register write enable).
Whether to read from or write to data memory (memory read/write enables).
Which multiplexer selects to activate (e.g., does the ALU’s second input come from a register or from an immediate value? Does the PC’s next value come from PC+1 or from a branch target?).

The control unit is an FSM

This is the deep connection between the sequential logic material and processor architecture. In a multicycle processor, the control unit is a finite state machine that sequences through states: fetch, decode, execute stages for each instruction type. Each state produces a different set of control signal outputs.

In a single-cycle processor, the control unit is purely combinational: the control signals are functions of the opcode bits only, and all operations happen in one clock cycle. But even here, the next-state logic for the processor as a whole (determining the next PC value) is sequential: the PC is a state register and the PC update logic is its next-state function.

The FSM design techniques covered in the sequential logic portion of the course (see the FSM design material) apply directly to control unit design: state diagrams, state tables, next-state and output equations, K-map minimisation. In practice, control units for real processors are complex FSMs with dozens of states and hundreds of output signals, but the principles are identical.

Key datapath components

Register file: A small memory array containing the architectural registers (e.g., 32 registers, each 32 bits). Two read ports (output two registers simultaneously) and one write port. The write happens on the clock edge; the reads are combinational (outputs update as soon as the address inputs change). The register file’s design enables the decode stage to read two source registers in parallel and the writeback stage to write one result.

ALU: Performs arithmetic and logical operations. Common operations: ADD, SUB, AND, OR, XOR, left/right shift, set-on-less-than. The operation is selected by a multi-bit control signal (ALUop). The ALU also produces a zero flag: if the result is all zeros, the zero flag is asserted, which the branch logic uses.

Multiplexers (MUXes): The datapath’s configurable switches. A 2-to-1 MUX selects one of two inputs based on a control signal. Used extensively:

ALU input MUX: select between register value and immediate (sign-extended constant from instruction).
PC input MUX: select between PC+1 (sequential) and branch/jump target.
Register write data MUX: select between ALU result and memory read data (for LOAD).

Memory: In a single-cycle processor, separate instruction and data memories (Harvard architecture) are used so that instruction fetch and data access can happen simultaneously in one cycle. In a multicycle processor, a single unified memory can serve both roles because accesses happen in different cycles.

Non-architectural registers (multicycle only): Additional registers between pipeline stages or between cycles hold intermediate results: the Instruction Register (IR) holds the fetched instruction, the Memory Data Register (MDR) holds data read from or to be written to memory, and temporary registers hold ALU outputs between stages.

Connecting back to the FSM material

The control unit of a multicycle processor is a Moore or Mealy FSM:

States correspond to the current step of instruction execution (fetch, decode, execute-add, execute-load-mem, execute-load-writeback, etc.).
Inputs include the opcode field of the instruction (from the IR) and possibly ALU flags (like the zero flag for branches).
Outputs are the control signals: ALUop, RegWrite, MemRead, MemWrite, MUX selects, PC write enable.
State transitions depend on the current state and the opcode. After decode, the FSM branches to different state sequences depending on whether the instruction is ADD, LOAD, STORE, or BEQZ.

The FSM for even a simple multicycle processor has 10-15 states. The design methodology (state diagram → state table → next-state logic → K-maps → implementation) is directly applicable, though in practice it is usually described as a state transition diagram rather than minimised gate-level logic.

See /modules/digital-electronics/13-processor-architecture/03-instruction-execution/ for a detailed walkthrough of how specific instructions use the datapath.