Multicycle Processor

Motivation

The single-cycle processor (see /modules/digital-electronics/13-processor-architecture/04-single-cycle-processor/) has three weaknesses: clock period dictated by the slowest instruction, redundant hardware (three adders, two memories), and no hardware reuse. The multicycle processor addresses all three.

Design philosophy

Break each instruction into multiple shorter steps, each executed in one clock cycle. The clock period is now determined by the slowest step, not the slowest instruction. Since each step does less work, the clock can be faster.

Instructions take a variable number of cycles depending on their complexity:

• Short instructions (e.g., ADD): fewer cycles.
• Medium instructions (e.g., BEQZ): more cycles (need to test register).
• Long instructions (e.g., LOAD): most cycles (need to access memory).

Hardware reuse

One memory serves both instructions and data: instruction access happens in cycle 1 (fetch), data access happens in later cycles (if needed). This is now a true von Neumann shared-memory model.

One ALU serves multiple purposes across different cycles:

• Cycle 1: compute PC+1 (or PC+branch-offset).
• Cycle 2 (decode): pass through register values.
• Cycle 3 (execute): perform the actual ALU operation (ADD, SUB, etc.) or compute a memory address.
• For branches: compute the branch target.

Two adders eliminated: the ALU replaces both the PC+1 adder and the branch target adder, time-multiplexed across different cycles. This is a significant saving because fast multi-bit adders are complex and expensive.

Additional hardware required

The multicycle design adds non-architectural state elements (registers) to hold values between cycles:

• Instruction Register (IR): holds the fetched instruction so that the instruction memory can be used for data access in later cycles.
• Memory Data Register (MDR): holds data read from memory before writing to the register file (for LOAD) or data to be written to memory (for STORE).
• Temporary registers (A, B): hold the two register values read from the register file during decode, freeing the register file for other operations.
• ALUOut register: holds the ALU result between the execute cycle and the writeback cycle.

Extra multiplexers are needed to share the ALU and memory between different data sources. The control unit must now generate MUX select signals that change from cycle to cycle.

The control unit becomes an FSM

Unlike the single-cycle processor’s combinational control, the multicycle control unit is a finite state machine with multiple states per instruction. The state transitions depend on the opcode:

State 0: Fetch

• IR ← mem[PC]; PC ← PC+1
• Transition to State 1.

State 1: Decode / Register Fetch

• A ← R[rs1]; B ← R[rs2]; ALUOut ← PC + sign-extend(offset) (prepare branch target, just in case)
• Transition based on opcode.

State 2-3: Execute ADD

• State 2: ALUOut ← A + B
• State 3: R[rd] ← ALUOut (writeback)
• Transition to State 0.

State 2-5: Execute LOAD

• State 2: ALUOut ← A + sign-extend(offset) (compute address)
• State 3: MDR ← mem[ALUOut] (memory read)
• State 4: R[rd] ← MDR (writeback)
• Transition to State 0.

State 2-4: Execute STORE

• State 2: ALUOut ← A + sign-extend(offset) (compute address)
• State 3: mem[ALUOut] ← B (memory write)
• Transition to State 0.

State 2: Execute BEQZ

• State 2: if (A == 0) PC ← ALUOut (the pre-computed branch target)
• Transition to State 0.

This FSM has about 10-15 states for this simple ISA. State transitions and outputs are specified in a state table, and the next-state logic can be minimised using the same techniques covered in the sequential logic module.

Performance trade-off

$\text{Time per instruction} = \text{CPI} \times T_{\text{clock}}$

where CPI is the average clocks per instruction.

Instruction	Cycles (single)	Cycles (multi)
ADD	1 (long)	3 (short)
LOAD	1 (long)	5 (short)
STORE	1 (long)	4 (short)
BEQZ	1 (long)	2 (short)

If we assume a mix of instructions with an average CPI of about 4, and the multicycle clock period is roughly 1/5 of the single-cycle period (since each step is 1/5 of the work), then:

$\text{Single-cycle time} \propto 1 \times 5 = 5$ $\text{Multicycle time} \propto 4 \times 1 = 4$

A modest improvement. But the multicycle advantage is not purely about raw speed: it is about hardware cost reduction (one memory, one ALU, fewer adders) and flexibility. For large systems, eliminating extra memories and wide adders saves significant chip area and power.

Limitations

The multicycle processor introduces overhead:

• Register propagation delay and setup/hold times are incurred at every step, not just once per instruction.
• Additional non-architectural registers add complexity and chip area.
• The control FSM is more complex to design and verify.

It also does not fundamentally increase throughput: one instruction still completes every N cycles on average. To improve throughput, we need pipelining (see /modules/digital-electronics/13-processor-architecture/06-pipelined-processor/).