Setup and Hold Time

The Fundamental Timing Parameters of Flip-Flops

For a D flip-flop to sample data correctly, the D input must satisfy two timing constraints relative to the active clock edge:

Setup time (t_su): The minimum time for which the D input must be stable before the active clock edge. If D changes within t_su of the edge, the FF may not capture the correct value.

Hold time (t_h): The minimum time for which the D input must remain stable after the active clock edge. If D changes within t_h of the edge, the data may not be reliably stored.

Propagation delay (t_p or t_pcq): The time from the clock edge until the Q output reflects the sampled D value. Measured from the clock edge to the point where Q has stabilised at the new value.

These are visualised in the timing diagram:

Why These Constraints Exist

Within the flip-flop, the clock edge triggers a sequence of internal events: a transmission gate closes, trapping charge on a storage node. The D input must be stable:

• Before the edge, so that the correct voltage has time to charge the internal node through the input path. The setup time accounts for the RC delay of this charging.
• After the edge, because the transmission gate does not close instantaneously. If D changes while the gate is still partially open, the wrong value may leak through (“hold time violation”).

If either constraint is violated, the FF enters a metastable state (covered in /modules/digital-electronics/07-flip-flop-applications-and-timing/06-metastability/).

System-Level Timing: Setup Time Constraint

Consider a synchronous system where the output of FF0 passes through combinational logic to the input of FF1:

On the rising edge of CLK, FF0 outputs Q₀ after a delay t_pcq (clock-to-Q propagation delay). This signal enters the combinational logic (CL), producing D₁ after a combinational delay t_pd. D₁ is the input to FF1. For FF1 to sample correctly, D₁ must be stable at least t_su before the next clock edge. The analysis therefore tracks the longest possible path (worst-case maximum propagation delays):

$T_c \geq t_{pcq} + t_{pd} + t_{su}$

Where:

• T_c is the clock period
• t_pcq is the maximum clock-to-Q delay of FF0
• t_pd is the maximum propagation delay through the combinational logic
• t_su is the setup time of FF1

This inequality determines the maximum clock frequency:

$f_{max} = \frac{1}{T_{c,min}} = \frac{1}{t_{pcq} + t_{pd} + t_{su}}$

Worked Example: Maximum Clock Frequency

A system uses FFs with t_pcq = 50 ps, t_su = 60 ps, t_h = 10 ps. The combinational logic between FFs has a worst-case delay t_pd = 300 ps. What is the maximum clock frequency?

$T_c \geq 50 + 300 + 60 = 410 \text{ ps}$

$f_{max} = \frac{1}{410 \times 10^{-12}} \approx 2.44 \text{ GHz}$

If the designer wants to clock at 3 GHz (T_c = 333 ps), the combinational logic must be redesigned such that:

$t_{pd} \leq T_c - (t_{pcq} + t_{su}) = 333 - (50 + 60) = 223 \text{ ps}$

This 77 ps reduction might require pipelining: inserting an additional register stage within the combinational logic to split the 300 ps path into two shorter paths.

Hold Time Constraint

While the setup constraint limits the maximum clock frequency, the hold time constraint is fundamentally different. The data at FF1’s D input must not change before t_h has elapsed after the clock edge. The analysis considers the shortest possible path (best-case minimum propagation delays, also called contamination delays):

$t_{cd} \geq t_h$

Where t_cd is the minimum delay from FF0’s clock edge to D₁ changing. This minimum is the sum of FF0’s minimum clock-to-Q delay (t_ccq, also called contamination delay) plus the minimum combinational logic delay:

$t_{ccq} + t_{cd,logic} \geq t_h$

Critical insight: hold time violations cannot be fixed by slowing the clock. Slowing the clock increases T_c, which helps setup but does nothing for hold: the data at D₁ still changes at the same time after the clock edge regardless of the clock period. If the minimum path delay is too small, you must add delay (buffer insertion) or redesign the circuit.

Why Hold Time Is Usually Easy to Satisfy

In modern FFs, the hold time is often designed to be 0 (or even negative, meaning D can change slightly before the edge). Additionally, the minimum clock-to-Q delay of a well-designed FF exceeds its own hold time (otherwise two FFs couldn’t be directly cascaded without violating hold). When t_h = 0, the hold constraint is trivially satisfied.

However, hold violations become a serious problem when clock skew is present (discussed in the next note /modules/digital-electronics/07-flip-flop-applications-and-timing/05-clock-skew/).

Contamination Delay Terminology

Some textbooks (notably Harris and Harris) distinguish:

• Propagation delay (t_pd, t_pcq): the maximum time for the output to settle.
• Contamination delay (t_cd, t_ccq): the minimum time before the output begins to change.

The setup constraint uses maximum delays (worst case: how late can data arrive?). The hold constraint uses minimum delays (worst case: how early can data change?). This asymmetry is central to static timing analysis.