Synchronous Counters | Digital Electronics

The Synchronous Counter Principle

A synchronous counter eliminates the ripple problem by connecting all flip-flop clock inputs to the same system clock. All FFs change state simultaneously (synchronously). The trade-off: more complex combinational logic is needed to generate the appropriate FF input signals.

Design Procedure for Synchronous Counters

The design follows the FSM procedure described in detail in /modules/digital-electronics/08-synchronous-state-machines/02-fsm-design-procedure/. For a counter, the procedure simplifies because the state sequence is predetermined.

Step 1: Write down the desired count sequence. Step 2: Determine the number of FFs needed. For n states, need ⌈log₂ n⌉ FFs. Step 3: Write the modified state transition table: current state columns, next state columns, and FF input columns. Step 4: For D-FFs, the FF input column is identical to the next state column (since D = Q’). Step 5: Derive the combinational logic for each FF input from the current state bits, using K-maps (unused states become don’t-cares).

Worked Example: 0-to-7 Binary Up-Counter

Design a 3-bit binary up-counter using D-type FFs.

State transition table (modified):

Current state	Next state	FF inputs
Q₂ Q₁ Q₀	Q₂’ Q₁’ Q₀’	D₂ D₁ D₀
0 0 0	0 0 1	0 0 1
0 0 1	0 1 0	0 1 0
0 1 0	0 1 1	0 1 1
0 1 1	1 0 0	1 0 0
1 0 0	1 0 1	1 0 1
1 0 1	1 1 0	1 1 0
1 1 0	1 1 1	1 1 1
1 1 1	0 0 0	0 0 0

For D-FFs, Dᵢ = Qᵢ’, so the FF input columns are identical to the next-state columns.

Deriving the logic:

For FF0 (D₀): By inspection, D₀ = Q̄₀. FF0 toggles on every clock edge: when Q₀ = 0, D₀ = 1 (next state = 1); when Q₀ = 1, D₀ = 0 (next state = 0). Thus D₀ = Q̄₀, which is simply a NOT gate from Q₀ back to D₀. For a T-type design, this FF would have T₀ = 1 permanently.

For FF1 (D₁): By inspection of the table, Q₁ toggles only when Q₀ = 1. When Q₀ = 0, Q₁ holds its value. This is an XOR relationship:

$D_1 = Q_1 \oplus Q_0 = \bar{Q}_1 Q_0 + Q_1 \bar{Q}_0$

Verify: Q₁Q₀ = 00 → D₁ = 0; 01 → D₁ = 1; 10 → D₁ = 1; 11 → D₁ = 0. These match the next-state entries for Q₁’.

For FF2 (D₂): Use a K-map:

\begin{array}{c|cccc} Q_2 \setminus Q_1Q_0 & 00 & 01 & 11 & 10 \\ \hline 0 & 0 & 0 & 1 & 0 \\ 1 & 1 & 1 & 0 & 1 \end{array}

From the K-map: $D_2 = Q_0 Q_1 \bar{Q}_2 + Q_2 \bar{Q}_1 + Q_2 \bar{Q}_0$

Or, factorising: $D_2 = Q_2 \oplus (Q_0 Q_1)$

That is: Q₂ toggles when both lower bits are 1 (Q₀Q₁ = 11); otherwise it holds. This XOR formulation is verified by the table: D₂ = Q₂ only when Q₀Q₁ = 11, and D₂ = Q̄₂ otherwise.

General pattern for an n-bit binary up-counter using T-FFs (if T-FFs are available):

T₀ = 1 (toggle every clock)
T₁ = Q₀ (toggle when lsb is 1)
T₂ = Q₀ · Q₁ (toggle when all lower bits are 1)
Tᵢ = Q₀ · Q₁ · … · Qᵢ₋₁ (AND of all lower-order outputs)

For D-FFs, the equivalent is Dᵢ = Qᵢ ⊕ Tᵢ (XOR current state with toggle condition).

Worked Example: Divide-by-6 Counter

Design a counter that counts 000 → 001 → 010 → 011 → 100 → 101 → 000 (counts 0-5, resets). Uses 3 FFs (states 6 and 7 are unused).

Current state Q₂Q₁Q₀	Next state Q₂’Q₁’Q₀’
0 0 0	0 0 1
0 0 1	0 1 0
0 1 0	0 1 1
0 1 1	1 0 0
1 0 0	1 0 1
1 0 1	0 0 0
1 1 0	X X X (unused)
1 1 1	X X X (unused)

For D-FFs, plot K-maps with unused states as don’t-cares (X), allowing maximal simplification.

K-map for D₂:

\begin{array}{c|cccc} Q_2 \setminus Q_1Q_0 & 00 & 01 & 11 & 10 \\ \hline 0 & 0 & 0 & 1 & 0 \\ 1 & 1 & 0 & X & X \end{array}

D₂ = Q₀Q₁Q̄₂ + Q₂Q̄₀. Or: D₂ = Q₂ ⊕ (Q₀Q₁) with the unused states giving flexibility.

K-map for D₁: By inspection from the table (or a K-map), D₁ = Q̄₁Q₀ + Q₁Q̄₀ = Q₁ ⊕ Q₀ (same as the 0-7 counter).

K-map for D₀:

\begin{array}{c|cccc} Q_2 \setminus Q_1Q_0 & 00 & 01 & 11 & 10 \\ \hline 0 & 1 & 0 & 0 & 1 \\ 1 & 1 & 0 & X & X \end{array}

D₀ = Q̄₀Q̄₂ + Q̄₁Q̄₀ = Q̄₀(Q̄₂ + Q̄₁). Or equivalently: D₀ = Q̄₂·Q̄₀ + Q̄₀·Q̄₁ (the count resets when reaching 101, forcing Q₀ to 0).

Timing Advantage of Synchronous Counters

In a synchronous counter, all FFs change simultaneously. After a single propagation delay from the clock edge, all outputs are valid. The maximum clock frequency is:

$f_{max} \leq \frac{1}{t_{p\_CO} + t_{pd}(combinational) + t_{su}}$

where t_{p_CO} is the clock-to-Q delay of one FF, t_pd(combinational) is the worst-case delay through the next-state logic, and t_su is the setup time of the receiving FF. This does not depend on the number of bits n (except that the fan-in of the AND gate for the MSB grows with n, increasing t_pd modestly). Contrast with the ripple counter: f_max ≤ 1/(n·t_{p_CO}), which scales inversely with n.

Arbitrary Count Sequences

The same design procedure works for any count sequence. Write the desired sequence, fill the transition table, treat unused states as don’t-cares, and minimise using K-maps. This is the same procedure used for general FSM design, making the counter a special case of a finite state machine where the state sequence is predefined.