Examinable Syllabus and Tripos Question Patterns | Digital Electronics

Course overview

Course name: Digital Electronics
Paper: Part IA Paper 2, Questions 1 and 2 (typically Question 1 combinational logic, Question 2 sequential and electronics/processor)
Term: Michaelmas (lectures) with hardware labs running through Lent
Lecturer: Dr Ian Wassell
Format: Two questions on Paper 2; each worth 20 marks

Examinable topics

The course splits cleanly into the two Paper 2 questions. Question 1 is combinational logic; Question 2 is sequential logic, electronics and processor architecture. The lists below track the syllabus as delivered in the 2023 to 2026 lecture sets and cross-reference where each topic has been tested in the past.

Combinational logic (Q1 territory)

Boolean algebra: identity, commutation, association, distribution, absorption, the consensus theorem; proving and simplifying expressions using these laws (and by expanding each term to include one instance of every variable).
DeMorgan’s theorem: rewriting expressions to switch between AND/OR forms; converting a circuit into NAND-only or NOR-only implementations using bubble logic.
Logic minimisation: truth tables, minterms and maxterms, disjunctive and conjunctive normal forms (DNF/CNF), sum-of-products and product-of-sums.
Karnaugh maps: 3- and 4-variable maps, SOP and POS simplification, don’t-care conditions, multiple equal-complexity minimal forms.
Quine-McCluskey method: tabular minimisation, prime implicants, cyclic covering tables, counting equal-complexity solutions.
Binary adders: half and full adder, ripple carry adder, carry generate/propagate/kill signals, carry lookahead.
Multilevel logic and hazards: common expression elimination, gate propagation delay, static-1/static-0 and dynamic hazards, hazard removal by adding a consensus term.
Beyond simple gates: multiplexers and demultiplexers, decoders, memories and ROMs, PLA and PAL, tristate buffers and bus contention. Multiplexer-only implementations of arbitrary Boolean functions are examined regularly (a function of $n$ inputs can be realised by a $2^n{:}1$ MUX with the function values on the data lines, or by smaller MUXes using variables as select signals).

Frequently tested: Boolean algebra simplification, K-maps including don’t cares, Q-M with multiple equal solutions (2018 Q1, 2022 Q1, 2024 Q1), XOR identities and representing a function as the XOR of AND terms (2022 Q1, 2024 Q1, 2025 Q1), MUX implementation (2020 Q1).

Sequential logic (Q2 territory)

Latches: cross-coupled NOR/NAND RS latch, truth table, state diagram, illegal condition.
Clocked and D-type devices: transparent D-latch (built from an RS latch and steering logic), master-slave D flip-flop (edge triggering from two latches in series), JK and T flip-flops, asynchronous preset and clear.
Flip-flop applications: ripple and synchronous counters, shift registers, serial links.
Timing: setup and hold time constraints, clock skew, metastability and resolution probability (the bounded-but-random settling time of a flip-flop driven into its metastable region). Calculation of maximum clock frequency from path delays, and of minimum operating period given setup/hold times.
Synchronous state machines: Moore versus Mealy, state diagrams and state tables, FSM design procedure, state assignment strategies (sequential, sliding, shift register, one-hot). Worked examples: traffic light controller and past Tripos FSMs.
State machine optimisation: row matching, state equivalence, the implication table.

Frequently tested: D-FF next-state logic for counters with a mode input and self-start verification (2019 Q2, 2023 Q2, 2024 Q2), FSM state diagram and table from a problem description, state assignment and simplified D-input/output equations (2025 Q2, 2018 Q2), RS latch truth tables and D-latch construction from NOR gates (2017 Q2, 2018 Q2), state equivalence / implication table (2023 Q2, 2024 Q2), timing analysis of cascaded FF and combinational block paths with given setup/hold/propagation delays (2025 Q2).

Electronics, transistors and CMOS (Q2)

Basic electricity: voltage, current, resistance, power, Ohm’s law ( $V = IR$ ), Kirchhoff’s voltage and current laws, potential dividers.
Materials: insulators, conductors, silicon, doping to produce n-type and p-type semiconductors.
pn junction and diode: forward and reverse bias, threshold voltage.
MOSFET operation: n-channel and p-channel structure, gate controlling the drain-source current, characteristic curves of $I_{DS}$ against $V_{DS}$ for various $V_{GS}$ .
nMOS inverter with a resistor load: load line analysis on the MOSFET characteristics, finding $V_{out}$ for given $V_{in}$ , calculating resistor value and power dissipation (the standard worked example with a lookup table of $V_{DS}$ and $I_{DS}$ values).
CMOS inverter and CMOS gates (NAND, NOR): transistor-level diagrams, sizing for symmetric switching, noise margin.
Logic families: voltage transfer characteristics, $V_{OH}$ , $V_{OL}$ , $V_{IH}$ , $V_{IL}$ , noise margin $NM_H$ and $NM_L$ .

Frequently tested: draw n-channel MOSFET structure and explain $I_{DS}$ control (2015 Q2, 2012 Q2), nMOS inverter circuit and load-line plot of $V_{in}$ against $V_{out}$ , R and power calculation from a $V_{DS}$ / $I_{DS}$ table (2021 Q2, 2015 Q2, 2012 Q2). Examples paper 3 explicitly excludes rise and fall time calculations, so those are out of scope for Tripos revision.

Processor architecture (Q2)

Architecture vs microarchitecture: the distinction between the architectural view (instructions, registers, programmer-visible state) and the microarchitectural view (datapath and control).
Simple computer: CPU, memory, buses.
Single-cycle processor: datapath including PC, instruction memory, register file, ALU, data memory and writeback; control signals per instruction type.
Modifying the single-cycle datapath to support data memory access instructions, and to support branching.
Multicycle processor: reusing the ALU and memory across cycles, microcoded control, CPI greater than 1.
Pipelined processor: pipeline stages IF/ID/EX/MEM/WB, throughput benefits versus single-cycle and multicycle.
Pipeline hazards: data hazards and control hazards; the names of solutions (stalling, forwarding, predict not-taken, branch delay slot) and the trade-offs at a conceptual level.

Tested via examples paper 3 Q7 wording: “Explain the terms architecture and microarchitecture when applied to a processor. Show how the microarchitecture of a simple single cycle processor can be modified to permit data memory access / branching. What are the main advantages of a multicycle processor over a single cycle processor? How does a pipelined processor improve performance compared to a multicycle processor?” Past Paper 2 Tripos questions cited as relevant: 2023 Q2, 2021 Q2, 2019 Q2, 2015 Q2, 2012 Q2 (excluding rise and fall time calculations).

Non-examinable material

The following are part of the course but explicitly not tested in the written paper:

Hardware practical labs (breadboard prototyping, the prototyping box, SSI/MSI/GAL wiring exercises). Covered in Hardware Labs Overview.
HDL design flow beyond block-diagram level: synthesis, place and route and bitstream generation are taught conceptually, not examined at the level of vendor toolchains.
Detailed forwarding/stall logic, branch prediction algorithms and out-of-order hazards are reserved for the Part IB Computer Architecture course.
Rise and fall time calculations for CMOS (per Examples Paper 3 footnote).
FSM implementation technology specifics such as exact GAL device part numbers, Xilinx Spartan product families beyond the simplified CLB taught in lectures, or third-party FPGA tool features.

Standard Q1 pattern (combinational logic)

Part	Marks	Type	What to do
(a)	4 to 8	Boolean algebra	Simplify an expression into SOP or POS, prove an XOR identity, show a function equals XOR of AND terms
(b)	4 to 8	Karnaugh map	Simplify a 4-variable function into SOP and/or POS, including don’t cares; identify multiple equal-complexity minimum forms
(c)	6 to 9	Quine-McCluskey	Reduce a function given as a sum of minterms; count the number of equal-complexity solutions
(sometimes)	6	Multiplexer / decoder	Implement a Boolean function using 8:1, 4:1, 2:1 MUXes with extra gates, or use a decoder as a building block

Strategy:

For Boolean algebra, write the laws you apply (distribution, absorption, DeMorgan) as you go; markers reward method, not just the final expression.
For K-maps, label the axes clearly, draw the groups, and write the resulting product term next to each group. When asked for “multiple solutions” you must draw two groupings that yield different expressions of equal weight; do not just rearrange the same groups.
For Q-M, present the table of implicants by index (number of 1s) and chain merges carefully; tick off used implicants in the cover table and state explicitly when there are multiple equal-cost covers.

Standard Q2 pattern (sequential, electronics, processor)

Q2 is wider-ranging than Q1 and typically blends two or three of the sub-areas above. Common shapes seen across 2015 to 2025:

Sequential-only Q2: design a counter with a mode input (state diagram, transition table, simplified D-input equations in SOP, self-start check), then design or reduce an FSM from a state table (state assignment, K-maps for next-state logic, sometimes implication-table state reduction).

Mixed sequential and timing: build a flip-flop or counter, then add a setup/hold/propagation timing analysis of two cascaded flip-flops with combinational blocks between them (compute the maximum clock frequency and verify the hold-time constraint).

Electronics-focused Q2: MOSFET characteristics, nMOS inverter circuit and load line, resistor value and power calculations from a $V_{DS}$ / $I_{DS}$ table.

Processor Q2 (examples paper 3): architecture vs microarchitecture discussion, modify the single-cycle datapath for data memory or branching, advantages of multicycle over single-cycle, pipelining over multicycle. Past papers will reference 2012 Q2, 2015 Q2 and so on for these.

Q2 part	Marks	Type	What to do
(a)	6 to 10	Counter / latch / FF design	State diagram, transition table, simplified SOP for D inputs, self-start verification
(b)	9 to 12	FSM design or state reduction	Build or reduce an FSM, assign states, derive D-input and output equations; OR implication-table reduction with a reduced state table
electronics	12 to 14	MOSFET and nMOS inverter	Structure, $I_{DS}$ vs $V_{DS}$ curves, load line, R and power
processor	8 to 12	Datapath / architecture	Modify single-cycle datapath, discuss multicycle and pipelining

Strategy:

For counter design, always draw the state diagram and write the state transition table before K-mapping; this is where most marks hide.
For self-start questions, list every unused encoding and confirm it leads (possibly in several steps) into the main counting sequence. A single sentence “all unused states reach S0 in at most two transitions” with the explicit transitions shown earns the marks.
For implication-table questions, do row matching first even if not asked; it shrinks the table and makes the implication table faster to draw and check. Mark Xs in the table clearly and show at least one sweep pass so the marker can see the algorithm converging.
For timing analysis, write down the worst-case path delay formula (clock-to-Q + combinational delay + setup time) and only then substitute numbers; an algebraic answer that is numerically wrong still earns most of the marks.
For electronics, plot the load line by overlaying $V_{RD} = V_{DD} - I R$ on the MOSFET characteristics and report $V_{out}$ at both $V_{in} = 0$ V and $V_{in} = V_{DD}$ . Power in the resistor uses $P = I^2 R$ or $P = V_R I$ ; power in the transistor uses $P_{\text{MOS}} = V_{DS} I_{DS}$ .

Past Paper 2 questions cited as relevant by the lecturer (Examples Papers 1 to 3):

Combinational logic (Examples Paper 1): Q1-2023, Q1-2022, Q1-2021, Q1-2020, Q1-2019, Q1-2018.
Sequential logic (Examples Paper 2): Q2-2023, Q2-2022, Q2-2020, Q2-2019, Q2-2018.
FSMs, electronics and processor (Examples Paper 3): Q2-2023, Q2-2021, Q2-2019, Q2-2015, Q2-2012 (excluding rise and fall time calculations).

Recommended revision order

Boolean algebra and DeMorgan, then K-maps with don’t cares. These underpin every other part of Q1 and the next-state logic of Q2.
Quine-McCluskey. Practice counting equal-cost solutions, since this is a near-annual sub-question.
Latches and flip-flops, then counters and shift registers. Self-start questions and mode-input counters are mechanical once the state diagram habit is in place.
FSM design and implication-table state reduction. The two skills (design up, reduce down) are tested together.
Timing analysis (setup/hold, clock skew, metastability). One careful worked example is usually enough to internalise the algebra.
Electronics and CMOS, last because it is rote-heavy: MOSFET operation, nMOS inverter load line, noise margin.
Processor architecture at the conceptual level only: the comparison table of single-cycle, multicycle and pipelined architectures, plus the two requested modifications to the single-cycle datapath.

Summary

Topic	Q	Examinable?	Hard parts
Boolean algebra	Q1	Yes	Choosing which law to apply; proving XOR identities
Karnaugh maps (with don’t cares)	Q1	Yes	Equal-complexity minima are easy to miss
Quine-McCluskey	Q1	Yes	Counting equal-cost covers
MUX/decoder implementations	Q1	Yes	Variable-as-select tricks for smaller MUXes
Hazards (static/dynamic)	Q1	Yes	The consensus term to add when removing hazards
Latches and flip-flops	Q2	Yes	RS illegal condition, master-slave edge triggering
Counters and shift registers	Q2	Yes	Self-start verification
FSM design + state reduction	Q2	Yes	Implication table sweeps
Timing (setup/hold, metastability)	Q2	Yes	Worst-case path algebra
Electronics and CMOS	Q2	Yes	Load line, R and power from $V/I$ tables
Processor architecture	Q2	Yes (conceptual)	Single-cycle modifications, multicycle vs pipelined comparison
Hardware labs	Either	No	Practical only
HDL flow specifics, vendor tooling	Q2	No	Beyond syllabus depth