Ripple Carry Adder

Chaining full adders

An n-bit binary adder adds two n-bit numbers $A = a_{n-1}...a_1 a_0$ and $B = b_{n-1}...b_1 b_0$, plus an initial carry-in $c_0$, producing an n-bit sum $S = s_{n-1}...s_1 s_0$ and a final carry-out $c_n$.

The simplest implementation chains n full adders: the carry-out of column i feeds the carry-in of column i+1.

For each bit position i:

$s_i = a_i \oplus b_i \oplus c_i$

$c_{i+1} = a_i \cdot b_i + (a_i \oplus b_i) \cdot c_i$

The initial carry-in $c_0$ is typically 0 for unsigned addition (or can be set to 1 for two’s complement subtraction via $A + \sim B + 1$).

Delay analysis

The critical path of a ripple carry adder runs through the carry chain. Each full adder must wait for the previous column’s carry-out before it can produce its own carry-out.

Let $t_{\text{carry}}$ be the carry propagation delay through one full adder (typically 2 gate delays: one AND + one OR from the $(a \oplus b) \cdot c_{in}$ path). For an n-bit adder, the worst-case delay from $a_0$, $b_0$, $c_0$ to the final $c_n$ is:

$T_{\text{ripple}} = n \cdot t_{\text{carry}}$

The sum bits settle earlier: $s_0$ is ready after one XOR delay from $a_0 \oplus b_0$ followed by one XOR delay from $(a_0 \oplus b_0) \oplus c_0$. But $s_{n-1}$ must wait for $c_{n-1}$ to settle through n-1 carry stages.

For the worst case, consider adding A = 1111, B = 0001, c0 = 0:

• Column 0: 1+1+0 → s0=0, c1=1
• Column 1: 1+0+1 → s1=0, c2=1
• Column 2: 1+0+1 → s2=0, c3=1
• Column 3: 1+0+1 → s3=0, c4=1

The carry ripples through every column. Other worst cases are A = 0000, B = 1111, c0 = 1 (or any pattern that forces carry propagation through all bits).

Maximum clock frequency

In a synchronous system, the clock period must accommodate the critical path. For a ripple carry adder used between two registers (flip-flops):

$T_c \geq t_{pcq} + t_{\text{ripple}} + t_{su}$

where $t_{pcq}$ is the clock-to-Q delay of the source register and $t_{su}$ is the setup time of the destination register. The maximum operating frequency is $f_{\max} = 1/T_c$.

For modest n (e.g., 32 bits), $t_{\text{ripple}}$ can be tens of nanoseconds, limiting the clock frequency. This is why faster adder architectures (carry lookahead, carry select, carry skip) were developed for high-performance processors.

When ripple carry is acceptable

Ripple carry adders are simple, use minimal hardware, and are acceptable when:

• n is small (e.g., 4-8 bits).
• The clock period is slow relative to the ripple delay.
• Power consumption is more important than speed (fewer gates switching).
• Area is the primary constraint.

For large n or high-speed designs, the O(n) carry delay is unacceptable, motivating the carry lookahead approach described in the next section.