I/O Hardware and Methods

The device hierarchy

I/O devices span a vast range of performance:

Device	Data rate	Typical use
Keyboard	10 B/s	Character input
Mouse	100 B/s	Pointer updates
Gigabit Ethernet	125 MB/s	Network I/O
NVMe SSD	3–7 GB/s	Storage
GPU	16–64 GB/s (PCIe)	Graphics/compute

The OS must manage devices whose speeds differ by nine orders of magnitude — from slow character devices to high-throughput DMA engines.

Programmed I/O (PIO)

The CPU directly controls every byte of data transfer. The device has a status register (busy/ready) and a data register. The CPU polls the status register in a loop:

while (status & DEVICE_BUSY);    // wait until ready
*data_reg = byte_to_send;        // write data

Advantages: Simple hardware (no interrupt controller needed). Predictable latency.

Disadvantages: The CPU wastes cycles polling (CPU-bound waiting). Terrible for slow devices — the CPU could do millions of instructions while waiting for a disk or network operation.

Interrupt-driven I/O

The CPU issues an I/O command to the device, then continues executing other processes. When the device completes the operation, it raises an interrupt. The CPU invokes the device’s Interrupt Service Routine (ISR), which copies the data and wakes any waiting process.

Advantages: No busy-waiting. The CPU is free for other work during I/O.

Disadvantages: Interrupt overhead (context switch, ISR execution) for every small transfer. For a high-speed device (e.g., 10 Gbps Ethernet), interrupt overhead can dominate CPU time.

Direct Memory Access (DMA)

For bulk transfers, the CPU offloads the entire operation to a DMA controller. The CPU tells the DMA controller: source address, destination address, byte count. The DMA controller transfers the data directly between the device and memory, without CPU involvement per byte. When the transfer completes, the DMA controller raises a single interrupt.

Advantages: CPU is free during the entire transfer, not just between bytes. One interrupt per transfer, not per byte.

Disadvantages: Requires DMA-capable hardware. DMA transfers compete with the CPU for memory-bus bandwidth (though modern memory controllers are sophisticated enough to arbitrate fairly). DMA controllers are a limited resource (one per chipset, or per PCIe device).

Comparison

Method	CPU involvement	Latency per byte	Best for
PIO	CPU moves every byte	High (CPU-bound)	Very slow devices, early boot, debugging
Interrupt-driven	CPU handles one interrupt per transfer	Medium (interrupt overhead)	Medium-speed devices (keyboard, mouse)
DMA	CPU sets up transfer; device touches memory directly	Low (one interrupt per bulk transfer)	High-speed bulk devices (disk, NIC, GPU)

The modern reality

Real systems use hybrids. A network card might use interrupt-driven I/O for low traffic, then switch to DMA (and interrupt coalescing — batching multiple completions into one interrupt) under high load to reduce CPU overhead.

Summary

• PIO: CPU polls/writes every byte — simple but CPU-inefficient.
• Interrupt-driven: CPU free during I/O; overhead per interrupt.
• DMA: bulk transfers without per-byte CPU involvement; one interrupt per bulk transfer.
• Modern systems dynamically switch between polling, interrupt-driven, and DMA based on load.