Logical vs Physical Addresses

Two address spaces

A modern computer maintains a distinction between the addresses a programme uses and the addresses the memory hardware sees:

• Logical address (virtual address): the address generated by the CPU during instruction execution. Every load, store, and instruction fetch uses a logical address.
• Physical address: the address presented to the memory controller, selecting a specific cell in a DRAM module.

The Memory Management Unit (MMU) sits between the CPU and the memory bus, translating logical addresses to physical addresses on every access.

The MMU’s job

When the CPU issues a load from logical address $v$, the MMU:

1. Checks the TLB for a cached translation of $v$.
2. If TLB hit: physical address $p$ is available immediately.
3. If TLB miss: the MMU walks the page table (in hardware on some architectures, in software on others) to find the mapping for $v$. The translation is cached in the TLB for future references.
4. The MMU also checks permission bits in the page-table entry — if the access violates permissions (e.g., writing a read-only page), a page fault is raised.
5. If all checks pass, the physical address $p$ is placed on the memory bus.

From the CPU’s perspective, the load instruction completes normally. The translation is transparent.

Why separation matters

The logical-physical separation provides:

1. Isolation: Process A’s logical address 0x1000 maps to physical frame 0xA000; Process B’s logical 0x1000 maps to frame 0xB000. They cannot interfere even though they use the same logical addresses.
2. Relocation: The OS can move a process’s pages to different physical frames without the process knowing. The page table is updated; logical addresses are unchanged.
3. Sparse addressing: A process can have a logical address space far larger than the physical memory allocated to it. Unmapped logical addresses cause page faults (or grow the stack/heap on demand).
4. Sharing: A single physical page (e.g., a shared library’s read-only code) can be mapped into multiple processes’ logical address spaces.

Address translation example

Consider a system with 4 KB pages and a page table for Process P:

Logical page	Physical frame	Permissions
0	3	Read-Write
1	7	Read-Only
2	—	Not Present

Logical address 0x0000_0FFF → page 0, offset 0xFFF → physical address = frame 3 × 4096 + 0xFFF = 0x3000 + 0xFFF = 0x3FFF.

Logical address 0x0000_1000 → page 1, offset 0x000 → physical address = frame 7 × 4096 = 0x7000.

Logical address 0x0000_2000 → page 2, offset 0x000 → page fault (page not present). The kernel must bring the page in from disk (or allocate a fresh zero page) before the instruction can proceed.

Logical address 0x0000_1400 → page 1, offset 0x400, with a write operation → page fault (write to read-only page). The kernel terminates the process with SIGSEGV.

Page size considerations

Typical page sizes are 4 KB (x86, ARM), though larger pages are supported (2 MB “huge pages”, 1 GB “gigantic pages”). Smaller pages reduce internal fragmentation (wasted space within a page) but increase the page table size. Larger pages increase internal fragmentation but reduce the number of page-table entries and improve TLB reach.

Summary

• Logical addresses are what the programme uses; physical addresses are what the RAM uses.
• The MMU translates between them on every access, using the TLB and page table.
• Separation enables isolation, relocation, sparsity, and sharing.
• A page-fault occurs when a logical address has no valid physical mapping or the access violates permissions.