Memory Protection: Base and Limit Registers

The problem

Without memory protection, Process A could write to addresses belonging to Process B (or the kernel), corrupting data, stealing information, or crashing the system. The OS must enforce address-space isolation: each process can only access its own memory.

Base and limit registers

The simplest hardware mechanism uses two registers:

• Base register: the smallest physical address that the process may access.
• Limit register: the size of the process’s legal address range.

On every memory access, the hardware (typically the MMU) checks:

$\text{base} \le \text{address} < \text{base} + \text{limit}$

If the check fails, the MMU raises an exception (a segmentation fault), and the kernel terminates the offending process.

The base and limit registers are kernel-mode-only — the MOV instructions that modify them are privileged. On a context switch, the kernel saves the outgoing process’s base and limit and loads the incoming process’s values, thereby switching the protected address space.

Logical-to-physical translation

With base-and-limit hardware, every address a process uses is logical (or virtual). The hardware adds the base register to every address before sending it to the memory bus:

$\text{physical address} = \text{base} + \text{logical address}$

Process A’s logical address 0 maps to physical address base_A; Process B’s logical address 0 maps to base_B. Each process sees a contiguous address space starting at zero.

Limitations

Base-and-limit protection is simple but inflexible:

• No growth: a process that needs more memory than limit must be killed, moved, or resized — all expensive.
• Contiguous allocation: the entire address space must be one contiguous block of physical memory, leading to external fragmentation.
• No sharing: two processes cannot share a subset of pages (e.g., shared libraries) without overlapping the entire segment.
• No sparse addressing: the entire limit region must be backed by physical memory, even if the process uses only scattered pages.

Evolution

Base-and-limit was used in early systems (e.g., the CDC 6600). Modern architectures use paging (see [/modules/os/05-paging-and-page-tables/](managing memory)) which provides per-page protection, sparsity, and sharing — at the cost of more complex hardware.

However, the conceptual model persists: every process has its own address space, and the hardware checks every access against a kernel-managed configuration before allowing it.

Summary

• Base and limit registers enforce per-process memory isolation with a simple bounds check on every access.
• The MMU translates logical addresses by adding the base register.
• The scheme requires contiguous physical allocation and cannot support sparse address spaces or fine-grained sharing.
• Modern systems use paging, which generalises the idea: instead of one base-limit pair, there is a page table with per-page protection.